The present invention relates generally to electronic circuits. More particularly, the present invention relates to a class A/B amplifier output stage.
Class A/B amplifier output stages are commonly used in practical applications having low operating power and low operating voltage requirements. For example, such class A/B output stages may be used in operational amplifiers for mobile devices, smoke detectors, sensors, portable instruments, and the like. The design of a class A/B output stage plays a significant role in the overall driving ability, power consumption, and operating voltage of the circuit. Developers often utilize Monticelli's class A/B output stage in low voltage, low power operational amplifier designs. FIG. 1 is a circuit diagram of a class A/B output stage 100 that incorporates the Monticelli design. In accordance with conventional techniques, the input signal(s) are fed into the output stage 100 as small signal current through the current sources (labeled IB1). Although this design is widely used, the minimum supply voltage (VDD) for output stage 100 is: VDD=2VT+3VDSsat, where VT is the threshold voltage for the output driver transistors and VDSsat is the drain-to-source voltage at saturation for the output driver transistors. In this context,
      VDS    sat    =                              2          ⁢          I                          μ          ⁢                                          ⁢                      Cox            ⁡                          (                              W                L                            )                                            =          Δ      ⁢                          ⁢              V        .            In this expression, I is the bias current, μ is the electron/hole mobility, Cox is the oxide capacitance, W is the transistor channel width, and L is the transistor channel length. For the sake of simplicity, VDSsat is denoted as ΔV for reference.
The Monticelli output stage uses a cascode translinear loop to control output driver quiescent current, in which the transistors in the loop must be biased in the saturation region. The quiescent current is controlled by the current mirror ratio associated with the translinear loop formation, where a moderate amount of quiescent current is inevitably needed because the transistors, including the output driver transistors, are biased in the saturation region. In FIG. 1, transistors M1-M4 form one translinear loop, and transistors M5-M8 form another translinear loop. In this regard,
            I      q        =                                                      (                              W                L                            )                        4                    /                                    (                              W                L                            )                        1                          ⁢                  I                      B            ⁢                                                  ⁢            1                              =                                                  (                              W                L                            )                        8                    /                                    (                              W                L                            )                        6                          ⁢                  I                      B            ⁢                                                  ⁢            1                                ,where
            (              W        L            )        2    =                              (                      W            L                    )                3            ⁢                          ⁢      and      ⁢                          ⁢                        (                      W            L                    )                5              =                            (                      W            L                    )                7            .      In these expressions, Iq is the quiescent current of the Monticelli output stage and
      (          W      L        )    nis the aspect ratio of the channel width to the channel length of transistor Mn.
Accordingly, it is desirable to have a class A/B output stage that provides high speed operation (simplicity without feedback), has low minimum operating voltage requirements, and draws little quiescent current during normal operation. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.